In today's semiconductor device manufacturing industry, the cost to fabricate these devices needs to lessen, the number of devices that can be fit onto a single chip needs to increase, and the power consumed by each of these devices needs to be reduced. In an effort to achieve these goals, semiconductor device manufacturers have started to use interlevel and intralevel dielectrics which have lower dielectric constants so that adjacent conductors can be placed closer together without increasing the interaction between these two adjacent lines. In addition, semiconductor device manufacturers are starting to incorporate copper metallization into these devices so as to increase device reliability and to decrease the resistance of these conductive lines.
However, there are problems with implementing copper metallization and with using lower dielectric constant materials (“low-k materials” or “low-k dielectrics”). Copper structures are not easily etched without damaging other device structures. To alleviate this problem, a damascene process, which creates recesses in the dielectric layer for the copper interconnects to be formed within, is being attempted by many semiconductor device manufacturers. This process typically involves forming a copper layer over the dielectric layer, which has via holes and interconnect patterns already formed in them, and within the via holes and interconnect patterns. This formation step can be accomplished by electrochemical deposition (plating) or by another deposition technique. After the copper is formed, the wafers are removed from the deposition or plating tool and placed in a chemical-mechanical polishing (“CMP”) device. The CMP process is utilized to remove any unwanted copper structures and to planarize the desired copper interconnect structures.
If the dielectric layer is formed of low-k material, a couple problems arise with regards to the integration of the copper structures with the low-k material. First, some low-k materials can not withstand the downward pressure that it must withstand from the polishing device during the polishing of the copper layer. Second, the low-k material may not be able to withstand the polishing process necessary to clear all of the copper from the surface of the low-k material. In other words, some overpolishing of the copper layer must be performed to assure that all of the copper is cleared from atop of the low-k material. However, during this overpolishing step, some portions of the low-k material will be subjected to this polishing. If the low-k material is not robust enough to withstand this polishing, an undesirable amount of the low-k material may be polished away. Third, some low-k materials have low electrical breakdown strength and high line-to-line electrical leakage properties when formed between two conductors. Hence, while the capacitive-type (or crosstalk type) interaction between the two adjacent lines is lessened by the low-k material situated between the two lines, the leakage between the two lines may be increased due to the electrical leakage properties of some low-k materials.
In light of this, a need has arisen for the integration of low-k materials and copper metallization while reducing the leakage between adjacent copper lines due to the electrical leakage properties of some low-k materials.